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- Week of 14 October 2019 to 20 October 2019
Digital system design with FPGA : implementation using Verilog and VHDL / Cem Ünsalan, Bora Tar.
Call no: TK7895.G36 U57 2017
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design / Stuart Sutherland.
Call no: TK7885.7 .S87 2017